1. Technical Field
Various embodiments generally relate to a self-refresh device, and more particularly to a technology for generating a self-refresh period by reflecting refresh characteristics of an actual cell in a semiconductor device.
2. Related Art
A memory cell of a dynamic semiconductor memory such as a dynamic random access memory (DRAM) stores data in a capacitive element. Due to leakage of charges from the capacitive element, the memory cell must be periodically refreshed. The refresh process performs the read operation for restoring a level of charges stored in the memory cell to an original state.
Different types of refresh methods have been developed. Generally, the auto refresh method is configured to use a refresh timer located outside of a memory chip. In this way, the memory chip can perform the refresh operation in response to a periodic refresh command from a controller.
The self-refresh method is configured to use a refresh timer located inside the memory chip. In this way, all the memory chips are configured to request a refresh start command from the controller.
Typically, it is impossible for the refreshed memory cell to access the normal read and write operations. After lapse of a predetermined time upon completion of one refresh operation, an active cycle may start an operation. In this case, the predetermined time is generally denoted by a refresh row cycle time (tRFC).
A leakage current of the cell is closely related with a temperature, the temperature is of importance to a refresh period. That is, a short self-refresh period is needed for a relative high temperature.
On the other hand, DRAM automatically makes a period in consideration of a predetermined time in which a capacitor of the cell can maintain cell data in a self-refresh mode, such that the DRAM performs a refresh operation. Therefore, when the DRAM cell is designed, the refresh period is designed in consideration of a minimum voltage (ΔVMIN) capable of being detected by a sense amplifier (sense-amp).
However, assuming that the charging capability of the cell is higher than a retention level of a minimum voltage (ΔVMIN) capable of being generally detected by the sense amplifier (sense-amp), a waste of the cell capability occurs. In contrast, assuming that DRAM has a shorter refresh period than the substantial charging capability of the cell, a larger amount of current can be consumed than the cell capability.
In other words, the refresh period must indicate slope characteristics during the retention time of cell data. However, diode characteristics of the Temperature Compensated Self-Refresh (TCSR) circuit are different from the retention time of the cell data due to a process skew. As a result, there is a specific region in which the refresh period is not matched with cell refresh characteristics.